Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP5309360
Kind Code:
B2
Abstract:
A PIN diode has an n− drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n− drift layer. The n− drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n− drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.
More Like This:
Inventors:
Hideki Fujii
Application Number:
JP2008198338A
Publication Date:
October 09, 2013
Filing Date:
July 31, 2008
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L21/329; H01L29/861; H01L27/04; H01L29/78; H01L29/868
Domestic Patent References:
| JP2007059801A | ||||
| JP2007158320A | ||||
| JP8316500A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa