To make it possible to arrange sufficient amount of capacitors by preventing the interference between the wiring of an on-chip decoupling capacitor cell and the common wiring of an integrated circuit, while satisfying the performance of the integrated circuit.

When an on-chip decoupling capacitor cell is inserted into an integrated circuit, it is detected whether the wiring in this cell and the general signal wiring of an integrated circuit short-circuit, and in case of short-circuiting, another on-chip decoupling capacitor cell 7 is used. This cell 7 uses a first metal layer of for a wiring 8 of a lateral direction, and a second metal layer for a wiring 9 of a longitudinal direction, and the wiring 8, 9 are connected via a contact 10. Since a general signal wiring 5 exists in the same first metal as the wiring 8, it is possible to avoid a short circuit with a wiring 9 of the second metal layer.