MANUFACTURE OF SEMICONDUCTOR DEVICE

Japanese Patent JP3114654

B2

PROBLEM TO BE SOLVED: To form with the minimum number of masks and to make identical the junction depth of the channel region of nMOS and pMOS transistors and that of source/drain, in a method for manufacturing a CMOS transistor.
SOLUTION: An element separation region 6 for subdividing a pMOS transistor formation region and an nMOS transistor formation region is formed on the substrate in SOI structure, and a gate insulation film 11 is formed at the pMOS and the nMOS transistor formation regions. After that, boron and arsenic are introduced into the pMOS and the nM0S transistor formation regions, a channel region 10 of the nMOS transistor and a source/drain region 16 of the nMOS transistor are formed at the nMOS transistor formation region by boron and arsenic, respectively, arsenic and boron are introduced to the pMOS transistor formation region selectively, and a channel region 8 and a source/drain region 18 of the pMOS transistor are formed at the pMOS transistor formation region.

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Kiyotaka Imai
Hideaki Ohnishi

JP14801697A

December 04, 2000

June 05, 1997

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NEC

H01L21/336; H01L21/762; H01L21/8238; H01L21/84; H01L27/092; H01L29/786; (IPC1-7): H01L21/8238; H01L21/336; H01L27/092; H01L29/786

JP6112483A
JP5267600A
JP4257267A
JP60154660A
JP575041A

Naoki Kyomoto (2 outside)

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