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Patent Searching and Data


Title:
DEMODULATING CIRCUIT FOR DELTA MODULATING SIGNAL
Document Type and Number:
Japanese Patent JPS5994939
Kind Code:
A
Abstract:

PURPOSE: To attain an excellent reproducing signal with less storage of a DC error component by constituting a cutoff frequency of an integrator of an input delta modulating signal so as to increase when error bits are numerous.

CONSTITUTION: A switch 19 of delta demodulators 13, 14 is connected in parallel with a resistor R1 of a feedback circuit 18, and when the switch 19 is closed, a low-frequency pass band of the circuit 18 is spread, the cutoff frequency functioning as the integrator is increased, and the DC error component caused by the bit error of the delta modulation signal is attenuated rapidly and the quality of the reproducing signal is improved. On the other hand, when the high cutoff frequency of the integrator is increased, since the low-frequency dynamic range of the reproduced analog signal is reduced, the switch 19 is opened for the normal delta modulation transmission so as to ensure the required dynamic range and the excellent reproducing signal is obtained by closing the switch 19 with the transmission where the error rate of the delta modulation is increased.


Inventors:
AKAGIRI KENZOU
Application Number:
JP20432982A
Publication Date:
May 31, 1984
Filing Date:
November 19, 1982
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03M3/02; H04B14/06; (IPC1-7): H03K13/22; H04B12/04
Attorney, Agent or Firm:
Tsuchiya Masaru