Title:
DEVICE AND METHOD FOR GATE DELAY CALCULATION
Document Type and Number:
Japanese Patent JP3925980
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve calculating precision by calculating the source resistance value of an RC model through the use of a parameter for expressing as the function of time and then calculating gate delay.
SOLUTION: A gate delay calculating device is provided with a parameter housing file 24 for previously housing a parameter expressing the source resistance value as the function of time. A source resistance value deciding part 21 obtains the parameter of the source resistance value to be necessitated at the time of calculating gate delay from an input waveform inclination 25 and an output load model 26 from a source resistance parameter file 24. A gate delay deciding part 22 decides gate delay from the source resistance parameter and the output load model 26. An input waveform deciding part 23 calculates input waveform data to be necessitated when a wiring delay calculating device calculates wiring delay. Thereby, the calculating accuracy of gate delay is improved by satisfactorily matching with the waveform of an actual source resistance value.
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Inventors:
Kuriyama Shigeru
Michio Furumoda
Michio Furumoda
Application Number:
JP4908697A
Publication Date:
June 06, 2007
Filing Date:
March 04, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F17/50; H01L21/82; G06F7/60; G06G7/48; (IPC1-7): G06F17/50; H01L21/82
Domestic Patent References:
| JP7239865A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai