Title:
積層型半導体装置
Document Type and Number:
Japanese Patent JP4237160
Kind Code:
B2
Abstract:
A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the connecting terminals and external terminals; semiconductor chips having a pad row in which pads is arranged linearly in parallel to the terminal row and being stacked on the baseboard; and interposer boards having a wiring layer including a plurality of wires arranged in parallel with the same length for connecting between pads of the pad row and connecting terminals of the terminal row.
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Inventors:
Mitsuaki Katagiri
Masanori Shibamoto
Atsushi Hara
Koichiro Aoki
Naoya Isada
Shuji Kikuchi
Naofumi Tanie
Masanori Shibamoto
Atsushi Hara
Koichiro Aoki
Naoya Isada
Shuji Kikuchi
Naofumi Tanie
Application Number:
JP2005112902A
Publication Date:
March 11, 2009
Filing Date:
April 08, 2005
Export Citation:
Assignee:
エルピーダメモリ株式会社
株式会社日立製作所
株式会社日立製作所
International Classes:
H01L25/065; H01L25/07; H01L25/10; H01L25/11; H01L25/18
Domestic Patent References:
| JP200533201A | ||||
| JP2004327474A | ||||
| JP200463777A | ||||
| JP2001110978A | ||||
| JP8167630A | ||||
| JP2002151644A | ||||
| JP2002289769A |
Attorney, Agent or Firm:
Kohei Shuto