Title:
METHOD FOR MANUFACTURE OF CMOS STRUCTURE
Document Type and Number:
Japanese Patent JPH04262570
Kind Code:
A
Abstract:
PURPOSE: To fabricate a CMOS structure which can be integrated by a BICMOS process by a method wherein a dielectric spacer, coming in contact with a gate electrode, a source and drain region are formed, the second nitride is formed on the structure, an oxide layer is formed thereon, and a source and drain contact is formed. CONSTITUTION: After the first part of a source and drain region 42 has been formed, a side wall spacer 44, which comes in contact with a gate electrode 40, is formed, and an N-type conductivity type source and drain region 42 is formed by injecting N-type dopant to a doped well 32A. Then, a homogenous nitride layer 46 is formed on the surface of a structure 30, a low temperature oxide layer 48 is deposited on a nitride layer 46 and the entire surface of the structure 30, and the oxide layer 48 is planarized on the gate region 40. Then, the contact of the source and drain against a CMOS device is formed. As a result, a CMOS structure which can be easily integrated can be fabricated by a BICMOS process.
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Inventors:
PIITAA JIEI ZEBERU
Application Number:
JP27499491A
Publication Date:
September 17, 1992
Filing Date:
September 27, 1991
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H01L21/336; H01L21/8238; H01L27/092; H01L27/06; (IPC1-7): H01L27/092
Attorney, Agent or Firm:
Shinsuke Onuki