Title:
MULTI-LAYER PACKAGED HYBRID INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0590484
Kind Code:
A
Abstract:
PURPOSE: To improve packaging density of a hybrid integrated circuit on which chip parts are mounted.
CONSTITUTION: A sealed chip part 8 is packaged in a hollow part 2 having a bottom of a multi-layer wiring board 1 with the hollow part 2 provided, a thick wiring board 3 is adhesively fixed to an upper opening of the hollow part 2, and a surface packaged part 7 is attached to a wiring conductor 9 of surface and rear faces of the entire body.
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Inventors:
TANAKA KATSUMI
Application Number:
JP27612691A
Publication Date:
April 09, 1993
Filing Date:
September 30, 1991
Export Citation:
Assignee:
KOKUSAI ELECTRIC CO LTD
International Classes:
H01L25/00; H05K1/00; H05K1/14; H05K1/18; (IPC1-7): H01L25/00
Attorney, Agent or Firm:
Manabu Otsuka (1 person outside)
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