Title:
SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP2023175740
Kind Code:
A
Abstract:
To suppress a drop in potential of a gate of a pull-up transistor, which is one of objects.SOLUTION: A first transistor included in a driver circuit has: a first terminal that is electrically connected to second wiring, a second terminal that is electrically connected to first wiring, and a gate that is electrically connected to a second circuit and a first terminal of a third transistor; a second transistor that has a first terminal that is electrically connected to the first wiring, a second terminal that is electrically connected to sixth wiring, and a gate that is electrically connected to a first circuit and a gate of the third transistor; and the third transistor that has a second terminal that is electrically connected to the sixth wiring. The first circuit is electrically connected to third wiring, fourth wiring, fifth wiring, and the sixth wiring, and the second circuit is electrically connected to the first wiring, the second wiring. and the sixth wiring.SELECTED DRAWING: Figure 1
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Inventors:
UMEZAKI ATSUSHI
Application Number:
JP2023144366A
Publication Date:
December 12, 2023
Filing Date:
September 06, 2023
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB CO LTD
International Classes:
H01L21/8234; G09G3/20; G09G3/36; G11C19/28; H01L21/82; H01L21/822; H01L29/786