Title:
半導体パッケージの製造方法
Document Type and Number:
Japanese Patent JP7487519
Kind Code:
B2
Abstract:
To provide a method for manufacturing a semiconductor package capable of stably securing electric connection between a ground contact point on a side surface of a rewiring layer and an electromagnetic wave shield layer even if a rewiring layer is as thin as less than 40 μm.SOLUTION: A method for manufacturing a semiconductor package includes an arranging step and a forming step. The arranging step arranges a plurality of semiconductor packages in a temporarily fixing film so that a circuit surface of the semiconductor package comes into contact with the temporarily fixing film and an interval between adjacent semiconductor packages becomes higher than or equal to 0.1 mm. The forming step forms an electromagnetic wave shield layer on surfaces of the plurality of semiconductor packages on the temporarily fixing film. Each semiconductor package includes a rewiring layer of less than 40 μm, and a ground contact point provided on a side surface of the rewiring layer. The arranging step arranges the plurality of semiconductor packages in the temporarily fixing film so that the ground contact point is not embedded in the temporarily fixing film.SELECTED DRAWING: Figure 4
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Inventors:
Shizu Fukuzumi
Naoya Suzuki
Naoya Suzuki
Application Number:
JP2020058791A
Publication Date:
May 21, 2024
Filing Date:
March 27, 2020
Export Citation:
Assignee:
Resonac Co., Ltd.
International Classes:
H01L21/56; H01L21/301; H01L23/00; H01L23/28
Domestic Patent References:
| JP2019009371A | ||||
| JP2017143210A |
Foreign References:
| WO2019167778A1 | ||||
| WO2020059572A1 | ||||
| WO2020032176A1 |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshinori Shimizu
Hiroyuki Hirano
Youhei Suzuki
Yoshinori Shimizu
Hiroyuki Hirano
Youhei Suzuki