To provide the constitution of a semiconductor storage device which automatically detects a defective memory cell through a self-test and can store the defect address corresponding to the defective memory cell without using a fuse circuit.

A BIST circuit 100 detects the defective memory cell by conducting an operation test of a memory cell array 30 when the power source is turned on. The BIST circuit 100 generates the redundant code of a faulty memory cell corresponding to the defective memory cell based on the result of the operation test. The redundant code is transmitted to a repair decision circuit 70 in a decoding circuit 40. The repair decision circuit 70 stores the redundant code in a volatile state while the power source is turned on. The repair decision circuit 70 accesses a corresponding spare memory cell area SRA when an input address ADD matches the internally stored redundant code.