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Patent Searching and Data


Title:
COMPLEMENTARY TYPE MOS SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS6021560
Kind Code:
A
Abstract:

PURPOSE: To attain the inhibition of latch-up phenomenon and the microformation of the element by a method wherein the substrate interface of at least of one element region of the first and second conductivity regions is provided with an impurity layer of the same conductivity type as that of said element region having a concentration at 1×1016/cm3 or more.

CONSTITUTION: This device has a structure wherein an element isolation region 104 is provided on a p type Si substrate 101, island-formed substrate regions 1051 and 1052 isolated by means of said region 104 being provided with a p type element region 18 and an n type one (n-well) 109 made of single crystal Si layers, respectively, and an n+ type single crystal Si layer 107 having a concentration of 1×1017/cm3 being then formed at the substrate 101 interface of the n type region 109. As a result, the resistance (ρs=2kΩ/square) of the n-well 109 can be more reduced by the Si layer 107, and the variation of potential in the well 109 can be inhibited; therefore the inhibition of latch-up is enabled.


Inventors:
MAEDA SATORU
IWAI HIROSHI
Application Number:
JP12891983A
Publication Date:
February 02, 1985
Filing Date:
July 15, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H01L27/08; H01L21/74; H01L21/76; H01L21/762; H01L21/8238; H01L29/78; H01L27/092; H01L27/105; (IPC1-7): H01L21/76; H01L27/08; H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue