Title:
A manufacturing method of a semiconductor device and a semiconductor device
Document Type and Number:
Japanese Patent JP6076020
Kind Code:
B2
Abstract:
A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm.
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Inventors:
Satoshi Uno
Hideaki Tsuchiya
Shinji Yokokawa
Hideaki Tsuchiya
Shinji Yokokawa
Application Number:
JP2012223966A
Publication Date:
February 08, 2017
Filing Date:
October 09, 2012
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/60; H01L23/12; H05K1/18; H05K3/34
Domestic Patent References:
| JP201196803A | ||||
| JP201129636A | ||||
| JP200860588A |
Foreign References:
| US8664760 |
Attorney, Agent or Firm:
Shinji Hayami
Satoshi Amagi
Satoshi Amagi
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