Title:
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME
Document Type and Number:
Japanese Patent JP2016126809
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of achieving low voltage operation and high-speed operation, and further to provide a method for driving the same.SOLUTION: In a semiconductor memory device, a flip-flop circuit is composed of two stages of inverters composed of TFETs. The flip-flop circuit comprises first and second nodes. The memory device includes a first access transistor composed of a TFET between the first node and a first write word line, and a second access transistor composed of a TFET between the second node and a second write word line. The memory device includes a MOS transistor whose gate is connected to the first node and supplying a voltage corresponding to an electric potential of the first node to a read bit line in response to a voltage applied to the read word line. The first and second access transistors are composed of TFETs connected so that a drain current flows from the first and second nodes to the write bit line when they enter an on-state.SELECTED DRAWING: Figure 1
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Inventors:
MIYANO SHINJI
Application Number:
JP2015000942A
Publication Date:
July 11, 2016
Filing Date:
January 06, 2015
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G11C11/413; G11C11/412
Attorney, Agent or Firm:
Sakai International Patent Office