Title:
METHOD FOR EVALUATING SILICON WAFER MANUFACTURING PROCESS AND SILICON WAFER MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2019/017190
Kind Code:
A1
Abstract:
Provided is a method for evaluating a silicon wafer manufacturing process by which a plurality of silicon wafers are mass-produced. A lifetime measurement of mass-produced silicon wafers is performed at different locations within the surface of each of the silicon wafers and a plurality of measurement values are obtained. A representative value for each silicon wafer is derived from the plurality of measurement values. The representative values of respective silicon wafers included in a wafer group are used to derive a determination threshold value for each wafer group composed of the plurality of silicon wafers. A determination is made as to whether the wafer group includes a silicon wafer which includes a lifetime error value set on the basis of the determination threshold value among the plurality of measurement values obtained for the respective silicon wafers, and a determination is made as to whether the manufacturing process is likely to generate defective items.
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Inventors:
DAIGO SHIGERU (JP)
MATSUDA SHUHEI (JP)
MATSUDA SHUHEI (JP)
Application Number:
PCT/JP2018/024986
Publication Date:
January 24, 2019
Filing Date:
July 02, 2018
Export Citation:
Assignee:
SUMCO CORP (JP)
International Classes:
H01L21/66; G01N22/00; H01L21/02
Foreign References:
JP2013197364A | 2013-09-30 | |||
JP2005301617A | 2005-10-27 | |||
JP2015032666A | 2015-02-16 | |||
JP2009302246A | 2009-12-24 | |||
JP2016056050A | 2016-04-21 | |||
JPH05129404A | 1993-05-25 | |||
JP2005051210A | 2005-02-24 |
Attorney, Agent or Firm:
SIKS & CO. (JP)
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